Performance-oriented placement and routing for field-programmable gate arrays

This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graphbased strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wirelength. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route a number of industrial benchmarks. -',;?:<; .-' I - ' I ',/ Switch Block

• Type: Conference
• Year: 1995
• Where: EURODAC
• Authors: Michael J. Alexander, James P. Cohoon, Joseph L. Ganley, Gabriel Robins
• Keywords: Channel Width, EURODAC 1995, Field-programmable Gate Arrays, Recursive Geometric Partitioning, VHDL