Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

37

ITC
1998
IEEE

favoriteEmaildiscussreport

77views Hardware» more ITC 1998»

Deterministic BIST with multiple scan chains

14 years 3 months ago

Deterministic BIST with multiple scan chains

Download www.iti.uni-stuttgart.de

A deterministic BIST scheme for circuits with multiple scan paths is presented. A procedure is described for synthesizing a pattern generator which stimulates all scan chains simultaneously and guarantees complete fault coverage. The new scheme may require less chip area than a classical LFSR-based approach while better or even complete fault coverage is obtained at the same time.

Gundolf Kiefer, Hans-Joachim Wunderlich

Real-time Traffic

Complete Fault Coverage | Deterministic Bist Scheme | Guarantees Complete Fault | Hardware | ITC 1998 |

claim paper

Related Content

» Deterministic BIST with Partial Scan

» ScanBIST A Multifrequency Scanbased BIST Method

» On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures

» Bist Reseeding with very few Seeds

» Gate Level Fault Diagnosis in ScanBased BIST

» Low Power BIST Based on Scan Partitioning

» A highly regular multiphase reseeding technique for scanbased BIST

» Effectiveness Improvement of ECR Tests

Post Info
More Details (n/a)

Added	05 Aug 2010
Updated	05 Aug 2010
Type	Conference
Year	1998
Where	ITC
Authors	Gundolf Kiefer, Hans-Joachim Wunderlich

Comments (0)