Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

19

JISE
2000

favoriteEmaildiscussreport

70views more JISE 2000»

Testing Configurable LUT-Based FPGAs

13 years 10 months ago

Testing Configurable LUT-Based FPGAs

Download www.iis.sinica.edu.tw

Shyue-Kung Lu, Jen-Sheng Shih

Real-time Traffic

JISE 2000 |

claim paper

Related Content

» Edgemap optimal performance driven technology mapping for iterative LUT based FPGA designs

» Configuration selftest in FPGAbased reconfigurable systems

» Testing the Configurable InterconnectLogic Interface of SRAMBased FPGAs

» A Test Procedure for Boundary Scan Circuitry in PLDs and FPGAs

» Soft Core Embedded Processor Based BuiltIn SelfTest of FPGAs

» BuiltIn SelfTest of Embedded SEU Detection Cores in Virtex4 and Virtex5 FPGAs

» Acceleration of FPGA Fault Injection Through MultiBit Testing

» BIST for Xilinx 4000 and Spartan Series FPGAs A Case Study

» Fault Grading FPGA Interconnect Test Configurations

Post Info
More Details (n/a)

Added	19 Dec 2010
Updated	19 Dec 2010
Type	Journal
Year	2000
Where	JISE
Authors	Shyue-Kung Lu, Jen-Sheng Shih

Comments (0)