Customized Instruction-Sets for Embedded Processors

It is generally believed that there will be little more variety in CPU architectures, and thus the design of Instruction-set Architectures (ISAs) will have no role in the future of embedded CPU design. Nonetheless, it is argued in this paper that architectural variety will soon again become an important topic, with the major motivation being increased performance due to the customization of CPUs to their intended use. Five major barriers that could hinder customization are described, including the problems of existing binaries, toolchain development and maintenance costs, lost savings/higher chip cost due to the lower volumes of customized processors, added hardware development costs, and some factors related to the product development cycle for embedded products. Each is discussed, along with potential, sometimes surprising, solutions. Keywords Embedded processors, custom processors, instruction-level parallelism, VLIW, mass customization of toolchains

• Type: Conference
• Year: 1999
• Where: DAC
• Authors: Joseph A. Fisher
• Keywords: CPU Architectures, DAC 1999, Design Automation, Hardware Development Costs, Keywords Embedded Processors