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ETS
2009
IEEE
128views Hardware» more  ETS 2009»
13 years 9 months ago
Algorithms for ADC Multi-site Test with Digital Input Stimulus
This paper reports two novel algorithms based on time-modulo reconstruction method intended for detection of the parametric faults in analogue-to-digital converters (ADC). In both ...
Xiaoqin Sheng, Hans G. Kerkhoff, Amir Zjajo, Guido...
ETS
2009
IEEE
98views Hardware» more  ETS 2009»
13 years 9 months ago
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is nee...
Stephan Eggersglüß, Rolf Drechsler
ETS
2009
IEEE
117views Hardware» more  ETS 2009»
13 years 9 months ago
A Two Phase Approach for Minimal Diagnostic Test Set Generation
We optimize the full-response diagnostic fault dictionary from a given test set. The smallest set of vectors is selected without loss of diagnostic resolution of the given test se...
Mohammed Ashfaq Shukoor, Vishwani D. Agrawal
ETS
2009
IEEE
99views Hardware» more  ETS 2009»
13 years 9 months ago
On Minimization of Peak Power for Scan Circuit during Test
Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current whic...
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, ...
ETS
2009
IEEE
79views Hardware» more  ETS 2009»
13 years 9 months ago
Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead
Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation. This paper improves concurrent BIST techniques based on a deterministic test ...
Michael A. Kochte, Christian G. Zoellin, Hans-Joac...