DAC
2011
ACM
13 years 13 days ago
2011
ACM
Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation te...
ISCAS
2003
IEEE
14 years 6 months ago
2003
IEEE
In this work a new test structure for mismatch characterization of CMOS technologies is presented. The test structure is modular, with a reduced area and it can be inserted in the...