Scheduling instruction effects for a statically pipelined processor

8 years 6 months ago

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Statically pipelined processors have a fully exposed datapath where all portions of the pipeline are directly controlled by eﬀects within an instruction, which simpliﬁes hardware and enables a new level of compiler optimizations. This paper describes an eﬀect scheduling strategy to aggressively compact instructions, which has a critical impact on code size and performance. Unique scheduling challenges include more frequent name dependences and fewer renaming opportunities due to static pipeline (SP) registers being dedicated for speciﬁc operations. We also realized the SP in a hardware implementation language (VHDL) to evaluate the real energy beneﬁts. Despite the compiler challenges, we achieve performance, code size, and energy improvements compared to a conventional MIPS processor. Keywords compiler, architecture, static pipeline, performance, energy

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