SEAT-LA: A Soft Error Analysis Tool for Combinational Logic

Radiation induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to develop techniques to quickly and accurately predict soft error rates (SER) in logic circuits. In this paper, we propose a new approach, which can be applied to designs that use cell libraries characterized for soft error analysis and utilizes analytical equations to model the propagation of a voltage pulse to the input of a state element. The average error of the SER estimates using our approach compared to the estimates obtained using circuit level simulations is 6.5% while providing an average speed up of 15000. We have demonstrated the scalability of our approach using designs from the ISCAS-85 benchmarks.

• Type: Conference
• Year: 2006
• Where: VLSID
• Authors: Jungsub Kim, Mary Jane Irwin, Narayanan Vijaykrishnan, R. Rajaraman, Yuan Xie
• Keywords: Average Error, Computer Architecture, Soft Error Analysis, Soft Error Rates, VLSID 2006