Sciweavers

DSN
2002
IEEE
14 years 4 months ago
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to...
Premkishore Shivakumar, Michael Kistler, Stephen W...
DATE
2008
IEEE
119views Hardware» more  DATE 2008»
14 years 5 months ago
Guiding Circuit Level Fault-Tolerance Design with Statistical Methods
In the last decade, the focus of fault-tolerance methods has tended towards circuit level modifications, such as transistor resizing, and away from expensive system level redunda...
Drew C. Ness, David J. Lilja
ICCD
2006
IEEE
138views Hardware» more  ICCD 2006»
14 years 8 months ago
Delay and Area Efficient First-level Cache Soft Error Detection and Correction
—Soft error rates are an increasing problem in modern VLSI circuits. Commonly used error correcting codes reduce soft error rates in large memories and second level caches but ar...
Karl Mohr, Lawrence Clark
VLSID
2003
IEEE
104views VLSI» more  VLSID 2003»
14 years 11 months ago
Analyzing Soft Errors in Leakage Optimized SRAM Design
Reducing leakage power and improving the reliability of data stored in the memory cells are both becoming challenging as technology scales down. While the smaller threshold voltag...
Vijay Degalahal, Narayanan Vijaykrishnan, Mary Jan...
VLSID
2006
IEEE
156views VLSI» more  VLSID 2006»
14 years 11 months ago
SEAT-LA: A Soft Error Analysis Tool for Combinational Logic
Radiation induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to deve...
Jungsub Kim, Mary Jane Irwin, Narayanan Vijaykrish...