CMOS Comparators for High-Speed and Low-Power Applications

— In this paper, we present two designs for CMOS comparators: one which is targeted for high-speed applications and another for low-power applications. Additionally, we present hierarchical pipelined comparators which can be optimized for delay, area, or power consumption by using either design in different stages. Simulation results for our fastest hierarchical 64-bit comparator with

• Type: Conference
• Year: 2006
• Where: ICCD
• Authors: Eric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri
• Keywords: CMOS Comparators, Hardware, Hierarchical 64-bit Comparator, Hierarchical Pipelined Comparators, ICCD 2006