Factoring and eliminating common subexpressions in polynomial expressions

Polynomial expressions are used to compute a wide variety of mathematical functions commonly found in signal processing and graphics applications, which provide good opportunities for optimization. However existing compiler techniques for reducing code complexity such as common subexpression elimination and value numbering are targeted towards general purpose applications and are unable to fully optimize these expressions. This paper presents algorithms to reduce the number of operations to compute a set of polynomial expression by factoring and eliminating common subexpressions. These algorithms are based on the algebraic techniques for multi-level logic synthesis. Experimental results on a set of benchmark applications with polynomial expressions showed an average of 42.5% reduction in the number of multiplications and 39.6% reduction in the number of clock cycles for computation of these expressions on the ARM processor core, compared to common subexpression elimination.

• Type: Conference
• Year: 2004
• Where: ICCAD
• Authors: Anup Hosangadi, Farzan Fallah, Ryan Kastner
• Keywords: Common Subexpression Elimination, Hardware, ICCAD 2004, Multi-level Logic Synthesis, Polynomial Expressions