The Y-Architecture for On-Chip Interconnect: Analysis and Methodology

The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions exploits onchip routing resources more efficiently than traditional Manhattan wiring architecture. This paper gives in-depth analysis of deployment issues associated with the Y-architecture. Contributions are as follows. (1) We analyze communication capability (throughput of meshes) for different interconnect architectures using a multicommodity flow approach and a Rentian communication model. Throughput of the Y-architecture is largely improved compared to the Manhattan architecture, and is close to the throughput of the X-architecture. (2) We propose a symmetrical Y clock tree structure with better path and total wire length compared to H clock tree. (3) We discuss power distribution under the Y-architecture, and give analytical and SPICE simulation results showing that the power network in Y-architecture can ...

• Type: Conference
• Year: 2003
• Where: ICCAD
• Authors: Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao
• Keywords: Clock Tree Structure, Hardware, ICCAD 2003, Manhattan Architecture, Manhattan Wiring Architecture