TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers

We present a new approach for TAM optimization and test scheduling in the modular testing of mixed-signal SOCs. A test planning approach for digital SOCs is extended to handle analog cores in a plug-and-play fashion. A test wrapper based on an ADC/DAC pair and a digital configuration circuit is designed for analog cores such that these cores can be accessed through digital TAMs. In this way, there is no dependence on an analog test bus and expensive mixed-signal testers. Experimental results are presented for several ITC’02 SOC test benchmarks to which three analog cores are added. The results show that the testing of analog cores can be interleaved with the testing of digital cores to reduce the overall testing time for a mixed-signal SOC.

• Type: Conference
• Year: 2003
• Where: ICCAD
• Authors: Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
• Keywords: Analog Cores, Analog Test Bus, Digital Cores, Hardware, ICCAD 2003