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ICCAD
2001
IEEE

On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits

14 years 9 months ago
On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits
This paper attempts to determine the capabilities of existing Redundancy Addition and Removal (SRAR) techniques for logic optimization of sequential circuits. To this purpose, we compare this method with the Retiming and Resynthesis (RaR) techniques. For the RaR case the set of possible transformations has been established by relating them to STG transformations by other authors. Following these works, we first formally demonstrate that logic transformations provided by RaR are covered by SRAR as well. Then we also show that SRAR is able to identify transformations that cannot be found by RaR. This way we prove the higher potential of the Sequential Redundancy Addition and Removal over the Retiming and Resynthesis techniques.
Enrique San Millán, Luis Entrena, Jos&eacut
Added 17 Mar 2010
Updated 17 Mar 2010
Type Conference
Year 2001
Where ICCAD
Authors Enrique San Millán, Luis Entrena, José Alberto Espejo
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