Total sensitivity based dfm optimization of standard library cells

Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. How to design robust cells under variations plays a crucial role in the overall circuit performance and yield. In this paper we propose a comprehensive sensitivity metric which seamlessly incorporates effects from device criticality, lithographic proximity, and process variations. We develop first-order models to compute these sensitivities, and perform robust layout optimization by minimizing the total delay sensitivity to reduce the delay variation on the nominal process condition and by minimizing the performance gap between the fastest and the slowest delay corners to reduce the leakage current on the process corner. The results on industrial 45nm node standard cells show up to 76% improvement in non-rectangular delay variation under nominal process condition, 24% reduction in the delay difference betwee...

• Type: Conference
• Year: 2010
• Where: ISPD
• Authors: Yongchan Ban, Savithri Sundareswaran, David Z. Pan
• Keywords: Hardware, ISPD 2010, Nominal Process Condition, Process Variations, Standard Cells