VTS
2008
IEEE
14 years 6 months ago
2008
IEEE
Dealing with static and dynamic parameter variations has become a major challenge for design and test. To avoid unnecessary yield loss and to ensure reliable system operation a ro...
VTS
2008
IEEE
14 years 6 months ago
2008
IEEE
Timing-related defects are becoming increasingly important in nanometer technology designs. Small delay variations induced by crosstalk, process variations, powersupply noise, as ...
VTS
2008
IEEE
14 years 6 months ago
2008
IEEE
Unlike the top-down photolithographic CMOS VLSI process, cost-effective bulk fabrication of nanodevices calls for a bottom-up approach, generally called self-assembly. Selfassembl...
VTS
2008
IEEE
14 years 6 months ago
2008
IEEE
—Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significa...
VTS
2008
IEEE
14 years 6 months ago
2008
IEEE
— Higher chip densities and the push for higher performance have continued to drive design needs. Transition delay fault testing has become the preferred method for ensuring thes...
VTS
2008
IEEE
14 years 6 months ago
2008
IEEE
With increasing IC process variation and increased operating speed, it is more likely that even subtle defects will lead to the malfunctioning of a circuit. Various fault models, ...
VTS
2008
IEEE
14 years 6 months ago
2008
IEEE
VTS
2008
IEEE
14 years 6 months ago
2008
IEEE
VTS
2008
IEEE
14 years 6 months ago
2008
IEEE
Trace buffers are commonly used to capture data during in-system silicon debug. This paper exploits the fact that it is not necessary to capture error-free data in the trace buffe...