Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs

Abstract— Self-calibrating designs have recently gained momentum as an alternative to methods relying on worst-case characterisation of silicon [2], [4], [8]. So far, reliable operation of existing link checkers—double sampling flip-flops or codebased—is not ensured over the whole range of bit error rate. Therefore, bit error rates where the checker reliability is poor are avoided either by worst-case characterisation of the link error rate (such as for double sampling flip-flops), or by constraining the operating point controller to avoid such regions (such as for code-based checkers). This paper proposes a novel checker architecture that bridges the gap between low overhead and high robustness over the whole error rate range. Specifically, we show how to combine optimally double sampling flip-flops with a code-based checker (in point of reliability). The resulting checker enables simple, efficient, and reliability-agnostic operating point control policies.

• Type: Conference
• Year: 2007
• Where: ISQED
• Authors: Frederic Worm, Patrick Thiran, Paolo Ienne
• Keywords: Bit Error Rates, Error Rate, Hardware, ISQED 2007, Sampling flip-flops