In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
We have developed a function-level power estimation methodology for predicting the power dissipation of embedded software. For a given microprocessor core, we empirically build th...
Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag ...
In this paper, we introduce a new technique for modeling and solving the dynamic power management (DPM) problem for systems with complex behavioral characteristics such as concurr...
This paper presents a D/A converter with a 14-bit intrinsic linearity in 0.5?m CMOS technology, which has been designed using a systematic design methodology for current-steering ...
Geert Van der Plas, Jan Vandenbussche, Walter Daem...
The idea of Force-Directed Scheduling (FDS) was first introduced by Paulin and Knight to minimize the number of resources required in the high-level synthesis of high-throughput A...
Recently, intellectual property protection (IPP) techniques attracted a great deal of attention from semiconductor, system integration and software companies. A number of watermar...
Image computation is the key step in fixpoint computations that are extensively used in model checking. Two techniques have been used for this step: one based on conjunction of the...
In-Ho Moon, James H. Kukula, Kavita Ravi, Fabio So...
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...