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    ASPDAC
    1999
    ACM
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    Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion

    14 years 4 months ago
    Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion
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    Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani
    claim paper
    Added 02 Aug 2010
    Updated 02 Aug 2010
    Type Conference
    Year 1999
    Where ASPDAC
    Authors Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani
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