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35

ASPDAC
2007
ACM

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A Graph Reduction Approach to Symbolic Circuit Analysis

14 years 3 months ago

A Graph Reduction Approach to Symbolic Circuit Analysis

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A new graph reduction approach to symbolic circuit analysis is developed in this paper. A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially designed graph reduction process and a recursive sign determination algorithm. A symbolic analog circuit simulator is developed using a combination of these techniques. The simulator is able to analyze large analog circuits in the frequency domain. Experimental results are reported.

Guoyong Shi, Weiwei Chen, C.-J. Richard Shi

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Added	12 Aug 2010
Updated	12 Aug 2010
Type	Conference
Year	2007
Where	ASPDAC
Authors	Guoyong Shi, Weiwei Chen, C.-J. Richard Shi

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