A Graph Reduction Approach to Symbolic Circuit Analysis

A new graph reduction approach to symbolic circuit analysis is developed in this paper. A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially designed graph reduction process and a recursive sign determination algorithm. A symbolic analog circuit simulator is developed using a combination of these techniques. The simulator is able to analyze large analog circuits in the frequency domain. Experimental results are reported.

• Type: Conference
• Year: 2007
• Where: ASPDAC
• Authors: Guoyong Shi, Weiwei Chen, C.-J. Richard Shi
• Keywords: Analog Circuits, ASPDAC 2007, Graph Reduction, Graph Reduction Approach, Hardware