136 search results - page 1 / 28 » A Graph Reduction Approach to Symbolic Circuit Analysis |
ASPDAC
2007
ACM
14 years 3 months ago
2007
ACM
A new graph reduction approach to symbolic circuit analysis is developed in this paper. A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially designed ...
DAC
1999
ACM
14 years 3 months ago
1999
ACM
This paper presents a method to reduce the complexity of a linear or linearized (small-signal) analog circuit. The reduction technique, based on quality-error ranking, can be used...
DAC
2004
ACM
14 years 4 months ago
2004
ACM
—This paper proposes a novel approach to the exact symbolic analysis of very large analog circuits. The new method is based on determinant decision diagrams (DDDs) representing s...
ICCD
2006
IEEE
14 years 8 months ago
2006
IEEE
— Accurate estimation of worst-case crosstalk effects is critical for a realistic estimation of the worst-case behavior of deep sub-micron circuits. Crosstalk analysis models usu...
DATE
1998
IEEE
14 years 3 months ago
1998
IEEE
Partial Scan techniques have been widely accepted as an effective solution to improve sequential ATPG performance while keeping acceptable area and performance overheads. Several ...