With an ever-increasing portion of the delay in highspeed CMOS chips attributable to the interconnect, interconnect-circuit design automation continues to grow in importance. By t...
An e cient solution to the wire sizing problem WSP usingthe Elmoredelaymodelisproposed. Two formulations of the problem are put forth: in the rst, the minimum interconnect delay i...
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer siz...