Leakage-Aware Design of Nanometer SoC

– In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be simultaneously suppressed for effective energy reduction. New low-leakage circuit techniques based on multi-threshold-voltage (multi-Vt) and multi-oxide-thickness (multi-tox) standard single-gate and emerging double-gate MOSFET/FinFET technologies are presented in this paper. The leakage savings achieved with the techniques are characterized for a diverse set of logic and memory circuits that are widely used in systems-on-chips. The speed, active power, noise immunity, and area tradeoffs with the leakage reduction schemes are also evaluated.

• Type: Conference
• Year: 2007
• Where: ISCAS
• Authors: Volkan Kursun, Sherif A. Tawfik, Zhiyu Liu
• Keywords: Dielectric Leakage Currents, ISCAS 2007, Leakage Reduction Schemes, Nm Cmos Technologies