We present a methodology for the simulation of soft errors targeting future nano-technological devices. This approach efficiently scales the failure rate of individual devices according to cell area and considers the effect of multiple faults within a circuit. Furthermore this methodology measures circuit operation over a range of environments and consequently provides a means of targeting designs to the expected operating environment rather than worst case. We demonstrate the effect area has on circuit reliability and fault tolerance.
Christian J. Hescott, Drew C. Ness, David J. Lilja