Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction

Assessing IC manufacturing process fluctuations and their impacts on IC interconnect performance has become unavoidable for modern DSM designs. However, the construction of parametric interconnect models is often hampered by the rapid increase in computational cost and model complexity. In this paper we present an efficient yet accurate parametric model order reduction algorithm for addressing the variability of IC interconnect performance. The efficiency of the approach lies in a novel combination of low-rank matrix approximation and multi-parameter moment matching. The complexity of the proposed parametric model order reduction is as low as that of a standard Krylov subspace method when applied to a nominal system. Under the projection-based framework, our algorithm also preserves the passivity of the resulting parametric models.

• Type: Conference
• Year: 2005
• Where: DATE
• Authors: Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif
• Keywords: DATE 2005, Hardware, IC Interconnect Performance, Parametric Model Order, Parametric Models