Segmented Addressable Scan Architecture

This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consumption, and tester channel requirements. With minimal hardware overhead, the architecture provides at least an order of magnitude reduction to each of the above problems. The architecture relies on scan chain segmentation and multiple-hot decoders.

• Type: Conference
• Year: 2005
• Where: VTS
• Authors: Ahmad A. Al-Yamani, Erik Chmelar, Mikhail Grinchuck
• Keywords: Test Architecture, Test Data Volume, Test Power Consumption, VTS 2005