17 search results - page 1 / 4 » Self-Testing of FPGA Delay Faults in the System Environment |
IOLTS
2000
IEEE
14 years 3 months ago
2000
IEEE
We propose a procedure for self-testing of an FPGA programmed to implement a user-defined function. The procedure is intended to improve the detectability of FPGA delay faults. Th...
IPPS
2005
IEEE
14 years 4 months ago
2005
IEEE
Modern internet and telephone switches consist of numerous VLSI-circuits operating at high frequencies to handle high bandwidths. It is beyond question that such systems must cont...
ITC
1997
IEEE
14 years 3 months ago
1997
IEEE
: Accurate diagnosis is an essential requirement in many testing environments, since it is the basis for any repair or replacement strategy used for chip or system fault-tolerance....
ASYNC
2000
IEEE
14 years 3 months ago
2000
IEEE
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
FPGA
2010
ACM
14 years 5 months ago
2010
ACM
Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems t...