Statistical Timing Analysis Using Bounds

The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to the dependencies created by reconverging paths in the circuit. In this paper, we propose a new approach to statistical timing analysis which uses statistical bounds. First, we provide a formal definition of the statistical delay of a circuit and derive a statistical timing analysis method from this definition. Since this method for finding the exact statistical delay has exponential run time complexity with circuit size, we also propose a new method for computing statistical bounds which has linear run time complexity. We prove the correctness of the proposed bounds. Since we provide both a lower and upper bound on the true statistical delay, we can determine the quality of the bounds. The proposed methods were i...

• Type: Conference
• Year: 2003
• Where: DATE
• Authors: Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
• Keywords: DATE 2003, Hardware, Run Time Complexity, Statistical Delay, Statistical Timing Analysis