Two efficient methods to reduce power and testing time

Reducing power dissipation and testing time is accomplished by forming two clusters of don’t-care bit inside an input and a response test cube. New reordering scheme of scan latches is proposed to create the clusters of don’t-care bit, and two proposed reconfigured scan architecture guarantee to remove the clusters from the scan operation. The size of these clusters is directly proportional to the amount of power and testing time that is reduced. Results with ISCAS’89 benchmark circuits show good improvement in both power consumption and test time. Categories and Subject Descriptors B.8.1 [Hardware]: Reliability, Testing, and Fault-Tolerance General Terms Design, Reliability Keywords Reordering Scan Latches, Scan Architecture, Power, Testing Time

• Type: Conference
• Year: 2005
• Where: ISLPED
• Authors: Il-soo Lee, Tony Ambler
• Keywords: ISLPED 2005, Scan Architecture, Scan Latches, Testing Time