Whitespace redistribution for thermal via insertion in 3D stacked ICs

One of the biggest challenges in 3D stacked IC design is heat dissipation. Incorporating thermal vias is a promising method for reducing the temperatures of 3D ICs. The bonding styles between device layers impose certain restrictions to where thermal vias may be inserted. This paper presents a whitespace redistribution algorithm that takes bonding style into consideration to improve thermal via placement, which in turn reduces temperature.

• Type: Conference
• Year: 2007
• Where: ICCD
• Authors: Eric Wong, Sung Kyu Lim
• Keywords: Hardware, ICCD 2007, Thermal Vias, Turn Reduces Temperature, Whitespace Redistribution Algorithm