116 search results - page 17 / 24 » Beyond Graphs: A New Synthesis. |
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
—In modern sub-micron design, achieving low-skew clock distributions is facing challenges for high-performance circuits. Symmetric global clock distribution and clock tree synthe...
ASYNC
2001
IEEE
14 years 1 months ago
2001
IEEE
This paper presents a new approach to two-level hazardfree sum-of-products logic minimization. No currently available minimizers for single-output literal-exact two-level hazard-f...
ISPD
2009
ACM
14 years 4 months ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
LATIN
2010
Springer
14 years 2 months ago
2010
Springer
In this paper, we consider Steiner forest and its generalizations, prize-collecting Steiner forest and k-Steiner forest, when the vertices of the input graph are points in the Euc...
FPGA
1997
ACM
14 years 2 months ago
1997
ACM
Programmable logic architectures increase in capacity before commercial circuits are designed for them, yielding a distinct problem for FPGA vendors: how to test and evaluate the ...