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» 1995 high level synthesis design repository
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ICCD
2001
IEEE
124views Hardware» more  ICCD 2001»
14 years 4 months ago
High-Level Power Modeling of CPLDs and FPGAs
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
Li Shang, Niraj K. Jha
ISLPED
1995
ACM
100views Hardware» more  ISLPED 1995»
13 years 11 months ago
Simultaneous scheduling and binding for power minimization during microarchitecture synthesis
ABSTRACT { Sub-micron technologies and the increasing size and complexity of integrated components have aggravated the e ect of long interconnects and buses, compared to that of ga...
Aurobindo Dasgupta, Ramesh Karri
ISCAS
1995
IEEE
102views Hardware» more  ISCAS 1995»
13 years 11 months ago
Log-Domain Filters Based on LC Ladder Synthesis
Abstract. A design method is proposed for the synthesis of linear, high-order, continuous-time filters using a unique translinear integrator circuit. Unlike previous attempts at i...
D. Perry, Gordon W. Roberts
EURODAC
1995
IEEE
135views VHDL» more  EURODAC 1995»
13 years 11 months ago
A high performance VHDL simulator for large systems design
The requirements of large system design place great demands upon the performance and diagnostic capabilities of simulation. This paper explains how these requirements have been sa...
Steve Hodgson, Zak Shaar, Andy Smith
ASPDAC
1995
ACM
116views Hardware» more  ASPDAC 1995»
13 years 11 months ago
A datapath synthesis system for the reconfigurable datapath architecture
Abstract — A datapath synthesis system (DPSS) for the reconfigurable datapath architecture (rDPA) is presented. The DPSS allows automatic mapping of high level descriptions onto...
Reiner W. Hartenstein, Rainer Kress