306 search results - page 33 / 62 » A 3d-audio reconfigurable processor |
ISCAS
2006
IEEE
14 years 3 months ago
2006
IEEE
— This paper proposes a new reconfigurable architecture for multi-media and wireless communications. The proposed architecture addresses three critical design issues with the loo...
HASE
1997
IEEE
14 years 1 months ago
1997
IEEE
Abstract: We present a time-bounded state-based communication mechanism for dynamically reconfigurable embedded systems. The mechanism is a single-processor, low-overhead version o...
DATE
2002
IEEE
14 years 1 months ago
2002
IEEE
In this paper, we investigate the benefits of a flexible, application-specific instruction set by adding a run-time Reconfigurable Functional Unit (RFU) to a VLIW processor. Preli...
ERSA
2006
13 years 10 months ago
2006
Abstract-- In heterogeneous tiled System-on-Chip architectures a Network-on-Chip is used to transport messages between processing elements. A reconfigurable network interface is us...
RECONFIG
2008
IEEE
14 years 3 months ago
2008
IEEE
This paper describes an efficient arithmetic processor for elliptic curve cryptography. The proposed processor consists of special architectural components, the most important of...