306 search results - page 41 / 62 » A 3d-audio reconfigurable processor |
FPL
2006
Springer
13 years 11 months ago
2006
Springer
This paper presents an implementation of a high-performance network application layer parser in FPGAs. At the core of the architecture resides a pattern matcher and a parser. The ...
DATE
2002
IEEE
14 years 21 days ago
2002
IEEE
Future networked appliances should be able to download new services or upgrades from the network and execute them locally. This flexibility is typically achieved by processors tha...
IPPS
2000
IEEE
14 years 3 days ago
2000
IEEE
HeteroSort load balances and sorts within static or dynamic networks using a conceptual torus mesh. We ported HeteroSort to a 16-node Beowulf cluster with a central switch architec...
ISCA
2000
IEEE
13 years 11 months ago
2000
IEEE
High performance general-purpose processors are increasingly being used for a variety of application domains scienti c, engineering, databases, and more recently, media processing...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
Run-time reconfigurable logic is a very attractive alterative in the design of SoC. However, configuration overhead can largely decrease the system performance. In this work, we p...