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DAC
2000
ACM
14 years 8 months ago
Designing systems-on-chip using cores
Leading-edge systems-on-chip (SoC) being designed today could reach 20 Million gates and 0.5 to 1 GHz operating frequency. In order to implement such systems, designers are increa...
Reinaldo A. Bergamaschi, William R. Lee
DAC
2000
ACM
14 years 8 months ago
Test challenges for deep sub-micron technologies
The use of deep submicron process technologies presents several new challenges in the area of manufacturing test. While a significant body of work has been devoted to identifying ...
Kwang-Ting Cheng, Sujit Dey, Mike Rodgers, Kaushik...
ICCD
2004
IEEE
135views Hardware» more  ICCD 2004»
14 years 4 months ago
Design Methodologies and Architecture Solutions for High-Performance Interconnects
In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex System-on-Chip (SoC) designs. F...
Davide Pandini, Cristiano Forzan, Livio Baldi
CODES
2007
IEEE
14 years 1 months ago
Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions
High-end biomedical applications are a good target for specificpurpose system-on-chip (SoC) implementations. Human heart electrocardiogram (ECG) real-time monitoring and analysis ...
Iyad Al Khatib, Davide Bertozzi, Axel Jantsch, Luc...
ASPDAC
2006
ACM
105views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Speed binning aware design methodology to improve profit under parameter variations
—Designing high-performance systems with high yield under parameter variations has raised serious design challenges in nanometer technologies. In this paper, we propose a profit-...
Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saib...