68 search results - page 9 / 14 » A Configuration Concept for a Massively Parallel FPGA Archit... |
DAC
2003
ACM
14 years 8 months ago
2003
ACM
In this paper, we describe a set of compiler analyses and an implementation that automatically map a sequential and un-annotated C program into a pipelined implementation, targete...
SAMOS
2005
Springer
14 years 29 days ago
2005
Springer
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...
FCCM
2005
IEEE
14 years 1 months ago
2005
IEEE
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
—This paper presents a DAC architecture built on parallel current-steering sub-DAC entities. Two main novelties are explored: flexibility and smartness. Firstly, a number of avai...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
The purpose of this article is to propose a survey of possible approaches for implementing embedded reconfigurable gate arrays into secure circuits. A standard secure interfacing ...