714 search results - page 23 / 143 » A Decompression Architecture for Low Power Embedded Systems |
NOCS
2007
IEEE
14 years 3 months ago
2007
IEEE
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
DATE
1999
IEEE
14 years 1 months ago
1999
IEEE
This paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed m...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
—More and more processor manufacturers have launched embedded multicore processors for consumer electronics products because such processors provide high performance and low powe...
JEC
2006
13 years 8 months ago
2006
We present an overview of the Synchroscalar single-chip, multi-core processor. Through the design of Synchroscalar, we find that high energy efficiency and low complexity can be a...
ASPDAC
2004
ACM
14 years 14 days ago
2004
ACM
- Each year tens of billions of Dollars are wasted by the microelectronics industry because of missed deadlines and delayed design projects. These delays are partially due to desig...