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ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
14 years 6 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
ICC
2007
IEEE
109views Communications» more  ICC 2007»
14 years 3 months ago
Design Linear Multiuser Transmitters from Linear Multiuser Receivers
— Novel concepts are introduced for finding the relationship between multiuser detection (MUD) and multiuser transmission (MUT), so that the study in MUT can benefit from the w...
Lie-Liang Yang
ASPDAC
2007
ACM
122views Hardware» more  ASPDAC 2007»
14 years 1 months ago
A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications
- The use of reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such cores are being used for their flexibility, powerful functionality and low ...
Zhenyu Liu, Tughrul Arslan, Ahmet T. Erdogan
ASPDAC
2004
ACM
109views Hardware» more  ASPDAC 2004»
14 years 2 months ago
Design methodology for IRA codes
Channel coding is an important building block in communication systems since it ensures the quality of service. Irregular repeat-accumulate (IRA) codes belong to the class of Low-...
Frank Kienle, Norbert Wehn
DATE
2009
IEEE
138views Hardware» more  DATE 2009»
14 years 4 months ago
Hardware/software co-design architecture for thermal management of chip multiprocessors
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
Omer Khan, Sandip Kundu