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» A Distributed Control Path Architecture for VLIW Processors
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SIGCOMM
2009
ACM
14 years 2 months ago
Optimizing the BSD routing system for parallel processing
The routing architecture of the original 4.4BSD [3] kernel has been deployed successfully without major design modification for over 15 years. In the unified routing architectur...
Qing Li, Kip Macy
ISCA
2003
IEEE
157views Hardware» more  ISCA 2003»
14 years 25 days ago
Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage
Scaling of CMOS technology causes the power supply voltages to fall and supply currents to rise at the same time as operating speeds are increasing. Falling supply voltages cause ...
Michael D. Powell, T. N. Vijaykumar
PDPTA
1996
13 years 8 months ago
Performance of a Multiprocessor Multidisk CD-ROM Image Server
Professionals in various elds such as medical imaging, biology, and civil engineering require rapid access to huge amounts of image data. Multimedia interfaces further increase t...
Rolf Muralt, Benoit A. Gennart, Bernard Krummenach...
HPCA
2008
IEEE
14 years 8 months ago
Serializing instructions in system-intensive workloads: Amdahl's Law strikes again
Serializing instructions (SIs), such as writes to control registers, have many complex dependencies, and are difficult to execute out-of-order (OoO). To avoid unnecessary complexi...
Philip M. Wells, Gurindar S. Sohi
HPCA
2000
IEEE
13 years 12 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...