90 search results - page 7 / 18 » A Dynamically Adaptable Hardware Transactional Memory |
DATE
2010
IEEE
14 years 21 days ago
2010
IEEE
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
ICDCS
2008
IEEE
14 years 2 months ago
2008
IEEE
We introduce a Write-Once Read-Many (WORM) storage system providing strong assurances of data retention and compliant migration, by leveraging trusted secure hardware in close dat...
ISCAS
1999
IEEE
13 years 12 months ago
1999
IEEE
In this paper, we present the application of dynamic trellis diagrams (DTDs) to automatic translation of data flow graphs (DFGs) into highly optimized programs for digital signal ...
ISCA
2011
IEEE
12 years 11 months ago
2011
IEEE
As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include ...
PPOPP
2010
ACM
14 years 4 months ago
2010
ACM
Drawing inspiration from several previous projects, we present an ownership-record-free software transactional memory (STM) system that combines extremely low overhead with unusua...