68 search results - page 4 / 14 » A Family of Logical Fault Models for Reversible Circuits |
HASE
2007
IEEE
14 years 1 months ago
2007
IEEE
We study recent developments in quantum computing (QC) testing and fault tolerance (FT) techniques and discuss several attempts to formalize quantum logic fault models. We illustr...
DSD
2007
IEEE
14 years 1 months ago
2007
IEEE
With continuing increase in soft error rates, its foreseeable that multiple faults will eventually need to be considered when modeling circuit sensitivity and evaluating faulttole...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-toband-tunneling (BTBT) leakage, results in the large incr...
ETS
2006
IEEE
14 years 1 months ago
2006
IEEE
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
DATE
2002
IEEE
14 years 12 days ago
2002
IEEE
Models meant for logic verification and simulation are often used for ATPG. For custom digital circuits, these models contain many tristate devices, which leads to lower fault co...