36 search results - page 6 / 8 » A Fast Two-level Logic Minimizer |
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
The synchronous modeling paradigm provides strong execution correctness guarantees to embedded system design while making minimal environmental assumptions. In most related framew...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
— Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upset...
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a high-availability system architecture called INDRA — an INtegrated framework for Dependable and Revivable Architecture that enhances a multicore processor ...
ISLPED
2000
ACM
13 years 11 months ago
2000
ACM
In this paper we present a completely on-chip voltage regulation technique which promises to adjust the degree of voltage regulation in a digital logic chip in the face of process...
CIIA
2009
13 years 8 months ago
2009
In this paper, we present a new synthesis feature namely, "Xor matching", and the foldback product term synthesis for Complex Programmable Logic Devices (CPLD) architectu...