103 search results - page 10 / 21 » A Fault Modeling Technique to Test Memory BIST Algorithms |
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typ...
SPAA
2003
ACM
14 years 1 months ago
2003
ACM
The general problem of verifying coherence for shared-memory multiprocessor executions is NP-Complete. Verifying memory consistency models is therefore NP-Hard, because memory con...
TSE
2010
13 years 6 months ago
2010
— Web script crashes and malformed dynamically-generated web pages are common errors, and they seriously impact the usability of web applications. Current tools for web-page vali...
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
We propose a technique for compressing test vectors. The technique reduces test application time and tester memory requirements by utilizing part of the predecessor response in co...