103 search results - page 11 / 21 » A Fault Modeling Technique to Test Memory BIST Algorithms |
ATVA
2007
Springer
14 years 1 months ago
2007
Springer
Fault tree analysis is a traditional and well-established technique for analyzing system design and robustness. Its purpose is to identify sets of basic events, called cut sets, wh...
WMPI
2004
ACM
14 years 1 months ago
2004
ACM
Abstract. Many applications with large data spaces that cannot run on a typical workstation (due to page faults) call for techniques to expand the effective memory size. One such t...
HPCA
2006
IEEE
14 years 8 months ago
2006
IEEE
An important means of validating the design of commercial-grade shared memory multiprocessors is to run a large number of pseudo-random test programs on them. However, when intent...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
We present an approach to prevent overtesting in scan-based delay test. The test data is transformed with respect to functional constraints while simultaneously keeping as many po...
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
Loical defect diagnosis is a critical yet challenging process in VLSI manufacturing. It involves the identification of the defect spots in a logic IC that fails testing. In the la...