103 search results - page 5 / 21 » A Fault Modeling Technique to Test Memory BIST Algorithms |
CSREAESA
2009
13 years 8 months ago
2009
Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip...
VLSID
2005
IEEE
14 years 1 months ago
2005
IEEE
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...
VTS
2003
IEEE
14 years 1 months ago
2003
IEEE
Reseeding is used to improve fault coverage of pseudorandom testing. The seed corresponds to the initial state of the LFSR before filling the scan chain. The number of determinist...
ET
2002
13 years 7 months ago
2002
LVDS is the acronym for Low-Voltage-DifferentialSignaling and is described in both the ANSI/TIA/EIA644 and IEEE 1596.3 standards. High performance yet Low Power and EMI have made ...
DATE
1998
IEEE
14 years 1 days ago
1998
IEEE
Most memory test algorithms are optimized tests for a particular memory technology and a particular set of fault models, under the assumption that the memory is bit-oriented; i.e....