We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity...
Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Salu...
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
1 The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates t...
This paper presents a new test response compaction technique with any number of unknown logic values (X’s) in the test response bits. The technique leverages an X-tolerant respo...
In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some wellknown memory ...