103 search results - page 6 / 21 » A Fault Modeling Technique to Test Memory BIST Algorithms |
130
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VLSID
2002
IEEE
16 years 4 months ago
2002
IEEE
We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity...
141
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ICES
2000
Springer
15 years 7 months ago
2000
Springer
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
113
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DFT
2002
IEEE
15 years 9 months ago
2002
IEEE
1 The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates t...
131
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DAC
2005
ACM
15 years 6 months ago
2005
ACM
This paper presents a new test response compaction technique with any number of unknown logic values (X’s) in the test response bits. The technique leverages an X-tolerant respo...
143
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DFT
1999
IEEE
15 years 8 months ago
1999
IEEE
In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some wellknown memory ...