103 search results - page 7 / 21 » A Fault Modeling Technique to Test Memory BIST Algorithms |
TVLSI
1998
13 years 7 months ago
1998
Abstract—We introduce a technique for on-line built-in selftesting (BIST) of bus-based field programmable gate arrays (FPGA’s). This system detects deviations from the intende...
PTS
2007
13 years 9 months ago
2007
Black-box testing is a popular technique for assessing the quality of a system. However, in case of a test failure, only little information is available to identify the root-cause ...
DATE
2010
IEEE
14 years 26 days ago
2010
IEEE
Abstract—Built-In Self-Test (BIST) is less often applied to random logic than to embedded memories due to the following reasons: Firstly, for a satisfiable fault coverage it may...
ANSS
2001
IEEE
13 years 11 months ago
2001
IEEE
In this paper, we employ the finite state machine (FSM) model for networks to investigate fault identification using passive testing. First, we introduce the concept of passive te...
DDECS
2009
IEEE
13 years 11 months ago
2009
IEEE
Although the Neighborhood Pattern Sensitive Fault (NPSF) model is recognized as a high quality fault model for memory arrays, the excessive test application time cost associated wi...