107 search results - page 6 / 22 » A Fine-Grain Parallel Architecture Based on Barrier Synchron... |
CASES
2007
ACM
13 years 10 months ago
2007
ACM
Many MPSoC applications are loop-intensive and amenable to automatic parallelization with suitable compiler support. One of the key components of any compiler-parallelized code is...
ISCA
2011
IEEE
12 years 10 months ago
2011
IEEE
As the number of cores on a single-chip grows, scalable barrier synchronization becomes increasingly difficult to implement. In software implementations, such as the tournament ba...
MICRO
2010
IEEE
13 years 4 months ago
2010
IEEE
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common rec...
ISLPED
2006
ACM
14 years 20 days ago
2006
ACM
Interprocessor synchronization, while extremely important for ensuring execution correctness, can be very costly in terms of both power and performance overheads. Unfortunately, m...
EUROPAR
2009
Springer
13 years 10 months ago
2009
Springer
The Cell Broadband Engine (Cell BE) is a heterogeneous multi-core processor specifically designed to exploit thread-level parallelism. Its memory model comprehends a common shared ...