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» A Fully Pipelined XQuery Processor
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SCOPES
2005
Springer
14 years 1 months ago
Generic Software Pipelining at the Assembly Level
Software used in embedded systems is subject to strict timing and space constraints. The growing software complexity creates an urgent need for fast program execution under the co...
Daniel Kästner, Markus Pister
MICRO
2005
IEEE
136views Hardware» more  MICRO 2005»
14 years 1 months ago
Automatic Thread Extraction with Decoupled Software Pipelining
Until recently, a steadily rising clock rate and other uniprocessor microarchitectural improvements could be relied upon to consistently deliver increasing performance for a wide ...
Guilherme Ottoni, Ram Rangan, Adam Stoler, David I...
TVLSI
2008
120views more  TVLSI 2008»
13 years 7 months ago
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
14 years 1 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
14 years 1 months ago
ASIP architecture for multi-standard wireless terminals
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
Daniele Lo Iacono, J. Zory, Ettore Messina, N. Pia...