43 search results - page 6 / 9 » A Fully Pipelined XQuery Processor |
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents a hardware-based dynamic optimizer that continuously optimizes an application’s instruction stream. In continuous optimization, dataflow optimizations are p...
ARITH
2007
IEEE
14 years 1 months ago
2007
IEEE
The floating-point multiply-add fused (MAF) unit sets a new trend in the processor design to speed up floatingpoint performance in scientific and multimedia applications. This ...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
ARITH
2003
IEEE
14 years 27 days ago
2003
IEEE
This paper presents a 64-bit fixed-point vector multiply-accumulator (MAC) architecture capable of supporting multiple precisions. The vector MAC can perform one 64x64, two 32x32...
ISCA
2003
IEEE
14 years 27 days ago
2003
IEEE
Current-generation microprocessors are designed to process instructions with one and two source operands at equal cost. Handling two source operands requires multiple ports for ea...